Integrated circuit memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). A goal of DRAM cell design is to achieve high density with a cell density of 8F2, where F is the minimum printable feature size. DRAM cells provide good memory density, but are relatively slow. A minimum value of capacitance per cell is required to sense conventional DRAM cells. Thus, the capacitor poses a scalability challenge for DRAM cells for every forthcoming generation of reduced feature size F. The capacitor structure has become three-dimensional and complex, which adversely impacts fabrication and yield. A goal of SRAM cell design is high performance. SRAM cells are faster than DRAM cells, but the required area for SRAM cells is large. Six-transistor and four-transistor memory cells have a cell density range from about 50 F2 to about 100 F2.
Negative Differential Resistance (NDR) devices have been used to reduce the number of elements per memory cell. However, NDR devices tend to suffer from problems such as high standby power consumption, high operating voltages, low speeds and complicated fabrication processes.
F. Nemati and J. D. Plummer have disclosed a two-device thyristor-based SRAM cell (TRAM) that includes an access transistor and a gate-assisted, vertical thyristor. The disclosed vertical p+/n/p/n+ thyristor is operated in a gate-enhanced switching mode to provide the memory cell with SRAM-like performance and DRAM-like density. The performance of the TRAM cell depends on the turn-off characteristics of the vertical thyristor, and the turn-off characteristics depend on the stored charge and carrier transit time in the p-region of the p+/n/p/n+ thyristor. The turn-off characteristics for the vertical thyristor is improved from milliseconds to five nanoseconds by reverse biasing the thyristor for a write-zero operation and by using a gate to assist with discharging the stored charge to turn off the thyristor. Even so, the geometry and vertical height of the vertical thyristor's p-region limits the turn-off characteristics and the associated cell performance of the gate-assisted, vertical thyristor disclosed by Nemati and Plummer. The scalability of the TRAM cell and the ability to control the performance of the TRAM cell are also limited.
S. Okhonin et al. has proposed a SOI capacitor-less single-transistor DRAM cell that uses the state of the floating body charge to control the channel conductance of the transistor and define the memory state (“1” or “0”). DRAM-like operations were demonstrated using a number of methods to generate carriers in the floating body. However, the stored charge retention time (memory retention) in the proposed cell is sensitive to the device channel length and decreases with decreasing channel length. Additionally, the memory retention in the proposed cell is fundamentally dependent on the recombination time constants, and multiple mechanisms of recombination could be simultaneously operative. Thus, the memory retention for the proposed cell is expected to be both temperature and process sensitive. Therefore, a serious concern is the ability to control memory retention.
There is a need in the art to provide improved memory cells.